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| Ordering number : ENN7141 CMOS IC LC75810E, 75810T 1/8 to 1/10 Duty Dot Matrix LCD Display Controllers/Drivers Overview The LC75810E and LC75810T are 1/8 to 1/10 duty dot matrix LCD display controllers/drivers that support the display of characters, numbers, and symbols. In addition to generating dot matrix LCD drive signals based on data transferred serially from a microcontroller, the LC75810E and LC75810T also provide on-chip character display ROM and RAM to allow display systems to be implemented easily. Package Dimensions unit: mm 3151A-QFP100E [LC75810E] 23.2 80 81 51 50 14.0 Features * 100 1 0.65 (0.58) 0.3 30 31 Controls and drives a 5 x 7, 5 x 8, or 5 x 9 dot matrix LCD. 3.0max 17.2 0.15 * Supports accessory display segment drive (up to 80 segments) Display technique: 1/8-duty, 1/4-bias drive (5 x 7 dots, 6 x 7 dots) 1/9-duty, 1/4-bias drive (5 x 8 dots, 6 x 8 dots) 1/10-duty, 1/4-bias drive (5 x 9 dots, 6 x 9 dots) Display digits: 16 digits x 1 line (5 x 7 dots), 15 digits x 1 line (5 x 8 or 5 x 9 dots) 13 digits x 1 line (6 x 7, 6 x 8, or 6 x 9 dots) Display control memory CGROM: 240 characters (5 x 7, 5 x 8, or 5 x 9 dots) CGRAM: 16 characters (5 x 7, 5 x 8, or 5 x 9 dots) DCRAM: 64 x 8 bits ALATCH: 80 bits Continued on next page. * CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO. * 0.1 (2.7) SANYO: QFP100E unit: mm 3274-TQFP100 [LC75810T] 0.5 * 16.0 14.0 75 76 51 50 * 100 1 (1.0) (1.0) 26 0.5 0.2 25 0.125 1.2max 0.1 Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. 32902RM(OT)No.7141-1/54 14.0 16.0 SANYO: TQFP100 0.8 20.0 LC75810E/T Continued from preceding page. * Instruction function Display on/off control Smooth up, down, left, and right scrolling of the display Provides a backup function based on power saving mode The frame frequency of the common and segment output waveforms can be controlled by instructions. Built-in display contrast adjustment circuit Serial data input supports CCB format communication with the system controller Independent LCD driver block power supply VLCD Provides a RES pin for IC internal initialization. RC oscillator circuit * * * * * * * No.7141-2/54 LC75810E/T Pin Assignments (Top view) S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 80 COM10/S79 COM9/S80 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 VDD VLCD VLCD0 VLCD1 VLCD2 VLCD3 VSS OSC RES CE 81 51 50 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 LC75810E (QFP100E) 100 1 30 CL DI S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 75 31 S76 S77 S78 COM10/S79 COM9/S80 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 VDD VLCD VLCD0 VLCD1 VLCD2 VLCD3 VSS OSC RES CE CL DI 76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 51 50 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 LC75810T (TQFP100) 100 1 25 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 26 No.7141-3/54 LC75810E/T Specifications Absolute Maximum Ratings at Ta = 25C, VSS = 0V Parameter Maximum supply voltage Symbol VDD max VLCD max VIN1 Input voltage VIN2 VIN3 Output voltage Output current Allowable power dissipation Operating temperature Storage temperature VOUT1 VOUT2 IOUT1 IOUT2 Pd max Topr Tstg VDD VLCD CE, CL, DI, RES OSC VLCD1, VLCD2, VLCD3 OSC VLCD0, S1 to S80, COM1 to COM10 S1 to S80 COM1 to COM10 Ta = 85C Conditions Ratings -0.3 to +7.0 -0.3 to +11.0 -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VLCD + 0.3 -0.3 to VDD+ 0.3 -0.3 to VLCD + 0.3 300 3 200 -40 to +85 -55 to +125 V A mA mW C C V Unit V Allowable Operating Ranges at Ta = -40C to + 85C, VSS = 0V Parameter Symbol VDD Supply voltage Output voltage Input voltage Input high level voltage Input low level voltage Recommended external resistance Recommended external capacitance Guaranteed oscillation range Data setup time Data hold time CE wait time CE setup time CE hold time High level clock pulse width Low level clock pulse width Minimum reset pulse width VLCD VLCD0 VLCD1 VLCD2 VLCD3 VIH VIL Rosc Cosc fosc tds tdh tcp tcs tch tH tL tWRES VDD When the display contrast adjustment circuit is used. When the display contrast adjustment circuit is not used. VLCD0 VLCD1 VLCD2 VLCD3 CE, CL, DI, RES CE, CL, DI, RES OSC OSC OSC CL, DI CL, DI CE, CL CE, CL CE, CL CL CL RES Conditions Ratings min. 2.7 7.0 4.5 4.5 3/4 VLCD0 2/4 VLCD0 1/4 VLCD0 0.8 VDD 0 10 470 150 (Figure 2) (Figure 2) (Figure 2) (Figure 2) (Figure 2) (Figure 2) (Figure 2) (Figure 3) 160 160 160 160 160 160 160 1 300 600 typ. max. 6.0 10.0 10.0 VLCD VLCD0 VLCD0 VLCD0 6.0 0.2 VDD Unit V V V V V k pF kHz ns ns ns ns ns ns ns s No.7141-4/54 LC75810E/T Electrical Characteristics for the Allowable Operating Ranges Parameter Hysteresis Input high level current Input low level current Symbol VH IIH IIL VOH1 Output high level voltage VOH2 Output low level voltage VOL1 VOL2 VMID1 Output middle level voltage 1 VMID2 VMID3 Oscillator frequency fosc IDD1 IDD2 ILCD1 COM1 to COM10: IO = -100 A S1 to S80: IO = 20 A COM1 to COM10: IO = 100 A S1 to S80: IO = 20 A COM1 to COM10: IO = 100 A COM1 to COM10: IO = 100 A OSC: VDD: VDD: VLCD: ROSC = 10 k COSC = 470 pF Power saving mode VDD = 6.0 V Output open fOSC = 300 kHz Power saving mode VLCD = 10.0 V Current drain ILCD2 VLCD: Output open fOSC = 300 kHz When the display contrast adjustment circuit is used VLCD = 10.0 V Output open ILCD3 VLCD: fOSC = 300 kHz When the display contrast adjustment circuit is not used Note 1: Excluding the bias voltage generation divider resistors built into the VLCD0, VLCD1, VLCD2, VLCD3, and VSS pins. (See figure 1.) 200 400 450 900 A 5 700 1400 2/4 VLCD0 -0.6 3/4 VLCD0 -0.6 1/4 VLCD0 -0.6 210 300 CE, CL, DI, RES CE, CL, DI, RES: VI = 6.0 V CE, CL, DI, RES: VI = 0 V S1 to S80: IO = -20 A -5.0 VLCD 0-0.6 VLCD 0-0.6 0.6 0.6 2/4 VLCD0 +0.6 3/4 VLCD0 +0.6 1/4 VLCD0 +0.6 390 5 kHz V Conditions Ratings min. typ. 0.1VDD 5.0 max. Unit V A A V V VLCD CONTRAST ADJUSTER VLCD0 VLCD1 VLCD2 VLCD3 VSS Excluding these resistors To the common and segment drivers Figure 1 No.7141-5/54 LC75810E/T * When CL is stopped at the low level CE VIH 50% VIL VIH VIL tH tL tcp tcs tch CL DI VIH VIL tds * tdh When CL is stopped at the high level CE tL CL tH VIH 50% VIL VIH VIL tcp tcs DI tds tdh Figure 2 VIH VIL tch Block Diagram S80/COM9 S79/COM10 S78 COM1 COM8 COMMON DRIVER SEGMENT DRIVER ALATCH 80bits LATCH SCROLL COUNTER CGRAM 5 x 9 x 16 bits CGROM 5 x 9 x 240 bits DCRAM 64 x 8 bits VDD VLCD CONTRAST ADJUSTER INSTRUCTION DECODER VLCD0 VLCD1 VLCD2 VLCD3 VSS TIMING GENERATOR CLOCK GENERATOR INSTRUCTION REGISTER ADDRESS COUNTER ADDRESS REGISTER SHIFT REGISTER CCB INTERFACE RES OSC CL CE DI S1 No.7141-6/54 LC75810E/T Pin Functions Pin No. Pin S1 to S78 S79/COM10 S80/COM9 COM1 to COM8 OSC CE CL DI LC75810E 3 to 80 81 82 90 to 83 98 100 1 2 LC75810T 1 to 78 79 80 88 to 81 96 98 99 100 Segment driver outputs The S79/COM10 and S80/COM9 pins can be used as common driver outputs under the "set display technique" instruction. Common driver outputs Oscillator connection. An oscillator circuit is formed by connecting an external resistor and capacitor at this pin. Serial data transfer inputs. These pins are connected to the microcontroller. CE: Chip enable CL: Synchronization clock DI: Transfer data Reset signal input * When RES is low (VSS) - Display off S1 to S78 = "L" (VSS) S79/COM10 and S80/COM9 = "L" (VSS) COM1 to COM8 = "L" (VSS) RES Function Active level I/O Handling when unused OPEN - O - - H O I/O I I OPEN VDD GND - I 99 97 - Serial data transfer is disabled. - The OSC pin oscillator is stopped. * When RES is high (VDD) - Display on after a "display on/off control" (display on state setting) instruction is executed. - Serial data transfers are enabled. - The OSC pin oscillator operates. LCD drive 4/4 bias voltage (high level) supply pin. The level on this pin can be changed by the display contrast adjustment circuit. However, VLCD0 must be greater than or equal to 4.5 V. Also, external power must not be applied to this pin since the pin circuit includes the display contrast adjustment circuit. LCD drive 3/4 bias voltage (middle level) supply pin. This pin can be used to supply the 3/4 VLCD0 voltage level externally. LCD drive 2/4 bias voltage (middle level) supply pin. This pin can be used to supply the 2/4 VLCD0 voltage level externally. LCD drive 1/4 bias voltage (middle level) supply pin. This pin can be used to supply the 1/4 VLCD0 voltage level externally. Logic block power supply connection. Provide a voltage of between 2.7 and 6.0 V. LCD driver block power supply connection. Provide a voltage of between 7.0 and 10.0 V when the display contrast adjustment circuit is used and provide a voltage of between 4.5 and 10.0 V when the circuit is not used. Power supply connection. Connect to ground. L I GND VLCD0 93 91 - O OPEN VLCD1 VLCD2 VLCD3 VDD 94 95 96 91 92 93 94 89 - - - - I I I - OPEN OPEN OPEN - VLCD VSS 92 97 90 95 - - - - - - No.7141-7/54 LC75810E/T Block Functions * AC (Address counter) AC is a counter that provides the DCRAM address. The address is automatically modified internally, and the LCD display state is retained. DCRAM (Data control RAM) DCRAM is the RAM that is used to store display data expressed as 8-bit character codes. (These character codes are converted to 5 x 7, 5 x 8, or 5 x 9 dot matrix character patterns using CGROM or CGRAM.) DCRAM has a capacity of 64 x 8 bits, and can hold 64 characters. The table below lists the correspondence between the 6-bit DCRAM address loaded into AC and the display position on the LCD panel. * * For a 64 digits x 1 line display structure (For a "set display technique" instruction with 0Z1 = 0 and 0Z2 = 0) When the DCRAM address loaded into AC is 00H Display digit DCRAM address (hexadecimal) First line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 61 62 63 64 3C 3D 3E 3F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 However, when the display smooth scrolling is performed, the DCRAM address shifts as follows. Display digit DCRAM address (hexadecimal) First line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 61 62 63 64 Shift to the left 3D 3E 3F 00 by 1 character digit Display digit DCRAM address (hexadecimal) First line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 3F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 61 62 63 64 Shift to the right 3B 3C 3D 3E by 1 character digit Note that the display area on the LCD is display digits 1 to 16 on the first line when a display technique is 5 x 7, 5 x 8, or 5 x 9 dots, and it is display digits 1 to 13 on the first line when a display technique is 6 x 7, 6 x 8, or 6 x 9 dots. * For a 32 digits x 2 lines display structure (For a "set display technique" instruction with 0Z1 = 1 and 0Z2 = 0) When the DCRAM address loaded into AC is 00H Display digit DCRAM address (hexadecimal) First line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 29 30 31 32 1C 1D 1E 1F 3C 3D 3E 3F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 Second line 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 However, when the display smooth scrolling is performed, the DCRAM address shifts as follows. Display digit DCRAM address (hexadecimal) First line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 29 30 31 32 Shift to the left 1D 1E 1F 00 by 1 character digit 3D 3E 3F 20 29 30 31 32 Second line 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 1 First line 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Display digit DCRAM address (hexadecimal) 1F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 Second line 3F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 1 First line 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Shift to the right 1B 1C 1D 1E by 1 character digit 3B 3C 3D 3E 29 30 31 32 Shift to the up or 3C 3D 3E 3F down by 1 character digit 1C 1D 1E 1F Display digit DCRAM address (hexadecimal) 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 Second line 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 Note that the display area on the LCD is display digits 1 to 16 on the first line when a display technique is 5 x 7, 5 x 8, or 5 x 9 dots, and it is display digits 1 to 13 on the first line when a display technique is 6 x 7, 6 x 8, or 6 x 9 dots. No.7141-8/54 LC75810E/T * For a 16 digits x 4 lines display structure (For a "set display technique" instruction with 0Z1 = 0 and 0Z2 = 1) When the DCRAM address loaded into AC is 00H Display digit First line DCRAM address (hexadecimal) Third line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F Second line 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Fourth line 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F However, when the display smooth scrolling is performed, the DCRAM address shifts as follows. Display digit First line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 DCRAM address (hexadecimal) Shift to the left by Second line 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 10 1 character digit Third line 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 20 Fourth line 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 30 Display digit First line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DCRAM address (hexadecimal) Shift to the right by Second line 1F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1 character digit Third line 2F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E Fourth line 3F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E Display digit First line DCRAM address (hexadecimal) Third line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Second line 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F Shift to the up by 1 character digit Fourth line 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Display digit First line DCRAM address (hexadecimal) Third line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Second line 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Shift to the down by 1 character digit Fourth line 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F Note that the display area on the LCD is display digits 1 to 16 on the first line when a display technique is 5 x 7, 5 x 8, or 5 x 9 dots, and it is display digits 1 to 13 on the first line when a display technique is 6 x 7, 6 x 8, or 6 x 9 dots. Note 2: The DCRAM address is expressed in hexadecimal. Least significant bit Most significant bit LSB MSB DA1 DA2 DA3 DA4 DA5 Hexadecimal Hexadecimal DCRAM address DA0 Example: When the DCRAM address is 2EH DA0 0 DA1 1 DA2 1 DA3 1 DA4 0 DA5 1 Note 3: 5 x 7 dots 5 x 8 dots 5 x 9 dots 6 x 7 dots 6 x 8 dots 6 x 9 dots *** *** *** *** *** *** 16-digit display 16-digit display 16-digit display 13-digit display 13-digit display 13-digit display 5 x 7 dots. 4 x 8 dots. 3 x 9 dots. 6 x 7 dots. 6 x 8 dots. 6 x 9 dots. No.7141-9/54 LC75810E/T * * * * CGROM (Character generator ROM) CGROM is the ROM that is used to generate the 240 kinds of 5 x 7, 5 x 8, or 5 x 9 dot matrix character patterns from the 8-bit character codes. CGROM has a capacity of 240 x 45 bits. When a character code is written to DCRAM, the character pattern stored in the CGROM corresponding to the character code is displayed at the position on the LCD corresponding to the DCRAM address loaded into AC. CGRAM (Character generator RAM) CGRAM is the RAM to which user programs can freely write arbitrary character patterns. Up to 16 kinds of 5 x 7, 5 x 8, or 5 x 9 dot matrix character patterns can be stored. CGRAM has a capacity of 16 x 45 bits. ALATCH (Additional data latch) ALATCH is the latch that is used to store the ADATA display data for the accessory display. ALATCH has a capacity of 80 bits, and the stored display data is displayed directly without the use of CGROM or CGRAM. SC (Scroll counter) SC is the counter that is used to scroll the display in the left, right, up, or down directions in dot units. Since this function scrolls in dot units, it implements smooth scrolling. Reset Function The LC75810E and LC75810T are reset when a low level is applied to the RES pin at power on and, in normal mode. On a reset the LC75810E and LC75810T create a display with all LCD panels turned off. However, after a reset applications must set the contents of DCRAM, ALATCH, and CGRAM before turning on display with a "display on/off control" instruction since the contents of these memories are undefined. That is, applications must execute the following instructions. * Set display technique * DCRAM data write * ALATCH data write (If ALATCH is used.) * CGRAM data write (IF CGRAM is used.) * Set AC and SC addresses * Set display contrast (If the display contrast adjustment circuit is used.) After executing the above instructions, applications must turn on the display with a "display on/off control" instruction. Note that when applications turn off in the normal mode, applications must turn off the display with a "display on/off control" instruction. (See the detailed instruction descriptions.) Serial Data Transfer Format * When CL is stopped at the low level CE CL DI 0 1 1 1 0 0 1 0 D0 D1 D2 D3 D4 Instruction data Up to 144 bits D142 D143 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits * When CL is stopped at the high level CE CL DI 0 1 1 1 0 0 1 0 D0 D1 D2 D3 D4 Instruction data Up to 144 bits D142 D143 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits * * CCB address: 4EH D0 to D143: Instruction data The data is acquired on the rising edge of the CL signal and latched on the falling edge of the CE signal. When transferring instruction data from the microcontroller, applications must assure that the time from the transfer of one set of instruction data until the next instruction data transfer is significantly longer than the instruction execution time. No.7141-10/54 Instruction Table Execution time (4) Instruction D0 D1 * * *D55 D56 D57 * * * D79 D80 D81 *** D111 D112 D113 D114 D115 D116 D117 D118 D119 D120 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 Set display technique OZ1 OZ2 DW X X X X X DT1 DT2 FC 0 0 0 0 1 0 s Display on/off control DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 DG11 DG12 DG13 DG14 DG15 DG16 M A SC BU 0 0 1 0 0 s/27 s (5) Display scroll HS0 HS1 HS2 X X X X X VS0 VS1 VS2 VS3 X X X X R/L D/U X 0 0 0 1 1 27 s/162 s (6) Set AC and SC addresses X X X X X VA0 VA1 VA2 VA3 X X X X DA0 DA1 DA2 DA3 DA4 DA5 X X X X X HA0 HA1 HA2 0 0 1 0 0 27 s DCRAM data write (7) AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5 X X IM1 IM2 X 0 0 1 0 1 27 s/ti s (8) ALATCH data write AD1AD2* * *AD24 AD25AD26* * * AD56 AD57 AD58 AD59 AD60 AD61 AD62 AD63 AD64 AD65 AD66 AD67 AD68 AD69 AD70 AD71 AD72 AD73 AD74 AD75 AD76 AD77 AD78 AD79 AD80 X X X 0 0 1 1 0 0 s CGRAM data write (9) X X CD1 CD2 * * * CD32 CD33 CD34 CD35 CD36 CD37 CD38 CD39 CD40 CD41 CD42 CD43 CD44 CD45 X CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 WM X X 0 0 1 1 1 27 s/40.5 s (10) LC75810E/T Set display contrast CT0 CT1 CT2 CT3 X X X X CTC X X 0 1 0 0 0 0 s X: don't care Notes 4: The execution times listed here apply when fosc = 300 kHz. The execution times differ when the oscillator frequency fosc differs. Example: When fosc = 210 kHz = 232 s 210 210 ti s x 300 = ti x 1.43 s 40.5 s x 300 = 58 s 27 s x 300 210 = 39 s 162 s x 300 210 5: Note that when the power saving mode (BU = 1) is set, the execution time is 27 s (when fosc = 300 kHz). 6: The execution time must be seen as being 162 s (when fosc = 300 kHz) if another "display scroll" instruction is executed immediately after a preceding "display scroll" instruction. 7, 8: Note that the data format differs when a "DCRAM data write" instruction is executed in normal increment mode (IM1 = 1, IM2 = 0) or super-increment mode (IM1 = 0, IM2 = 1). Also note that the execution time is ti s (when fosc = 300 kHz) if a "DCRAM data write" instruction is executed in super-increment mode. (See detailed instruction descriptions.) 9, 10: Note that the data format differs when a "CGRAM data write" instruction is executed in double write mode (WM = 1). Also note that the execution time is 40.5 s (when fosc = 300 kHz) if a "CGRAM data write" instruction is executed in double write mode. (See detailed instruction descriptions.) No.7141-11/54 LC75810E/T Detailed Instruction Descriptions * Set display technique D128 OZ1 D129 OZ2 D130 DW *** Code D132 X D133 X D134 X D135 X D136 DT1 D137 DT2 D138 FC D139 0 D140 0 D141 0 D142 0 D143 1 D131 X X:don't care DT1, DT2: Set the display technique DT1 0 1 0 DT2 0 0 1 Display technique 1/8 duty, 1/4 bias drive 1/9 duty, 1/4 bias drive 1/10 duty, 1/4 bias drive Output pins S80/COM9 S80 COM9 COM9 S79/COM10 S79 S79 COM10 11: Sn (n = 79, 80): Segment output COMn (n = 9, 10): Common output FC: Set the frame frequency of the common and segment output waveforms FC 0 1 Frame frequency 1/8 duty, 1/4 bias drive f8[Hz] fosc 3072 fosc 1536 1/9 duty, 1/4 bias drive f9[Hz] fosc 3456 fosc 1728 1/10 duty, 1/4 bias drive f10[Hz] fosc 3840 fosc 1920 OZ1, OZ2: Set the display structure OZ1 0 1 0 OZ2 0 0 1 Display structure 64 digits x 1 line display structure 32 digits x 2 lines display structure 16 digits x 4 lines display structure 12: See block functions (DCRAM) DW: Set the dot font width DW 0 1 Dot font width 5-dot font width 6-dot font width Number of display digits 16 digits x 1 line (5 x 7 dots), 15 digits x 1 line (5 x 8 or 5 x 9 dots) 13 digits x 1 line (6 x 7, 6 x 8, or 6 x 9 dots) 13: * 5-dot font width (5 x 7, 5 x 8, or 5 x 9 dots) COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 S80/COM9 S79/COM10 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S71 S72 S73 S74 S75 S76 S77 S78 COM10/S79 COM9/S80 * 6-dot font width (6 x 7, 6 x 8, or 6 x 9 dots) COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 S80/COM9 S79/COM10 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 No.7141-12/54 LC75810E/T * Display on/off control *** Code D120 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG1 0 DG1 1 DG1 2 DG1 3 DG1 4 DG1 5 DG1 6 M A SC BU 0 0 1 0 M, A: Specifies the data to be turned on or off. M 0 0 1 1 A 0 1 0 1 Display operating state Both MDATA and ADATA are turned off. (The display is forcibly turned off, regardless of the DG1 to DG16 data.) Only ADATA is turned on. (The ADATA of display digits specified by the DG1 to DG16 data are turned on.) Only MDATA is turned on. (The MDATA of display digits specified by the DG1 to DG16 data are turned on.) Both MDATA and ADATA are turned on. (The MDATA and ADATA of display digits specified by the DG1 to DG16 data are turned on.) *14: MDATA, ADATA 5 x 7 dot matrix * **** 5 x 8 dot matrix ADATA * **** 5 x 9 dot matrix ADATA * **** ADATA *** MDATA *** MDATA * ** MDATA 6 x 7 dot matrix * **** 6 x 8 dot matrix ADATA * **** 6 x 9 dot matrix ADATA * **** ADATA * ** MDATA * ** MDATA * * * MDATA DG1 to DG16: Specifies the display digit. Display digit Display digit data 1 DG1 2 DG2 3 DG3 4 DG4 5 DG5 6 DG6 7 DG7 8 DG8 9 DG9 10 DG10 11 DG11 12 DG12 13 DG13 14 DG14 15 DG15 16 DG16 For example, if DG1 to DG8 are 1, and DG9 to DG16 are 0, then display digits 1 to 8 will be turned on, and display digits 9 to 16 will be turned off (blanked). SC: Controls the common and segment output pins. SC 0 1 Common and segment output pin states Output of LCD drive waveforms Fixed at the VSS level (all segments off) Note 15: When SC is 1, the S1 to S80 and COM1 to COM10 output pins are set to the VSS level, regardless of the M, A, and DG1 to DG16 data. BU: Controls the normal mode and power saving mode. BU 0 Mode Normal mode Power saving mode 1 (In this mode, the OSC pin oscillator is stopped, and the common and segment pins are set to the VSS level. In this mode, instructions other than the "display on/off control" and "set display contrast" instructions cannot be executed. Thus applications must set the IC to normal mode before executing any of the other instructions.) No.7141-13/54 LC75810E/T * Display scroll *** Code D120 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 HS0 HS1 HS2 X X X X X VS0 VS1 VS2 VS3 X X X X R/L D/U X 0 0 0 1 1 X: don't care HS0 to HS2: Set the amount of smooth scrolling to be applied to MDATA in the left/right direction. HS0 0 1 0 1 0 1 0 HS1 0 0 1 1 0 0 1 HS2 0 0 0 0 1 1 1 Amount of smooth scrolling to be applied to MDATA in the left/right direction No shift in either the left or right direction Shift 1 dot to the left or right. (The shift direction (left or right) is specified with the R/L data.) Shift 2 dots to the left or right. (The shift direction (left or right) is specified with the R/L data.) Shift 3 dots to the left or right. (The shift direction (left or right) is specified with the R/L data.) Shift 4 dots to the left or right. (The shift direction (left or right) is specified with the R/L data.) Shift 5 dots to the left or right. (The shift direction (left or right) is specified with the R/L data.) Shift 6 dots to the left or right. (The shift direction (left or right) is specified with the R/L data.) VS0 to VS3: Set the amount of smooth scrolling to be applied to MDATA in the up/down direction. VS0 0 1 0 1 0 1 0 1 0 1 0 VS1 0 0 1 1 0 0 1 1 0 0 1 VS2 0 0 0 0 1 1 1 1 0 0 0 VS3 0 0 0 0 0 0 0 0 1 1 1 Amount of smooth scrolling to be applied to MDATA in the up/down direction No shift in either the up or down direction Shift 1 dot to the up or down. (The shift direction (up or down) is specified with the D/U data.) Shift 2 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) Shift 3 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) Shift 4 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) Shift 5 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) Shift 6 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) Shift 7 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) Shift 8 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) Shift 9 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) (16) Shift 10 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) (17) Notes: 16: This shift cannot be used when MDATA is 5 x 7 or 6 x 7 dots. 17: This shift cannot be used when MDATA is 5 x 7, 5 x 8, 6 x 7 or 6 x 8 dots. R/L: Specifies the MDATA shift direction (left or right). R/L 0 1 MDATA shift direction (left or right) Shift left Shift right D/U: Specifies the MDATA shift direction (up or down). D/U 0 1 MDATA shift direction (up or down) Shift up Shift down 18 Example of the "display scroll" instruction execution Assume that a 32 digits x 2 lines display structure (OZ1 = 1, OZ2 = 0) has been set up with the "set display technique" instruction, and that the following data has been written to DCRAM with the "DCRAM data write" instruction. Display digit First line 1 A 2 B 1 3 C 2 4 D 3 5 E 4 6 F 5 7 G 6 8 H 7 9 I 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 J 9 K a L b M c N d O e P f Q g R h S i T j U k V l W m X n Y o Z p < q > r z s y t x u w v DCRAM data Second line 0 No.7141-14/54 LC75810E/T * Display state (1) With no shifting in any direction, left, right, up, or down. HS0 0 HS1 0 HS2 0 VS0 0 VS1 0 VS2 0 VS3 0 R/L X D/U X X: don't care (5 x 7 dot matrix) (6 x 7 dot matrix) * Display state (2) Shifted 3 dots to the left relative to display state (1) HS0 1 HS1 1 HS2 0 VS0 0 VS1 0 VS2 0 VS3 0 R/L 0 D/U 0 (5 x 7 dot matrix) (6 x 7 dot matrix) * Display state (3) Shifted 6 dots to the left relative to display state (1) HS0 0 HS1 1 HS2 1 VS0 0 VS1 0 VS2 0 VS3 0 R/L 0 D/U 0 Shifted 3 dots to the left relative to display state (2) HS0 1 HS1 1 HS2 0 VS0 0 VS1 0 VS2 0 VS3 0 R/L 0 D/U 0 (5 x 7 dot matrix) (6 x 7 dot matrix) No.7141-15/54 LC75810E/T * Display state (4) Shifted 4 dots to the up relative to display state (1) HS0 0 HS1 0 HS2 0 VS0 0 VS1 0 VS2 1 VS3 0 R/L 0 D/U 0 (5 x 7 dot matrix) (6 x 7 dot matrix) * Display state (5) Shifted 8 dots to the up relative to display state (1) HS0 0 HS1 0 HS2 0 VS0 0 VS1 0 VS2 0 VS3 1 R/L 0 D/U 0 Shifted 4 dots to the up relative to display state (4) HS0 0 HS1 0 HS2 0 VS0 0 VS1 0 VS2 1 VS3 0 R/L 0 D/U 0 (5 x 7 dot matrix) (6 x 7 dot matrix) * Display state (6) Shifted 3 dots to the left and 4 dots to the up relative to display state (1) HS0 1 HS1 1 HS2 0 VS0 0 VS1 0 VS2 1 VS3 0 R/L 0 D/U 0 (5 x 7 dot matrix) (6 x 7 dot matrix) No.7141-16/54 LC75810E/T * Display state (7) Shifted 6 dots to the left and 8 dots to the up relative to display state (1) HS0 0 HS1 1 HS2 1 VS0 0 VS1 0 VS2 0 VS3 1 R/L 0 D/U 0 Shifted 8 dots to the up relative to display state (3) HS0 0 HS1 0 HS2 0 VS0 0 VS1 0 VS2 0 VS3 1 R/L 0 D/U 0 Shifted 6 dots to the left relative to display state (5) HS0 0 HS1 1 HS2 1 VS0 0 VS1 0 VS2 0 VS3 0 R/L 0 D/U 0 Shifted 3 dots to the left and 4 dots to the up relative to display state (6) HS0 1 HS1 1 HS2 0 VS0 0 VS1 0 VS2 1 VS3 0 R/L 0 D/U 0 (5 x 7 dot matrix) (6 x 7 dot matrix) * Set AC and SC addresses pattern for SC.> D112 HA0 D113 HA1 D114 HA2 D115 X *** Code D128 DA0 D129 DA1 D130 DA2 D131 DA3 D132 DA4 D133 DA5 D134 X D135 X D136 X D137 X D138 X D139 0 D140 0 D141 1 D142 0 D143 0 X: don't care DA0 to DA5: DCRAM address DA0 LSB DA1 DA2 DA3 DA4 DA5 MSB Least significant bit Most significant bit HA0 to HA2: Dot address in the horizontal direction for the dot matrix character pattern HA0 LSB HA1 HA2 MSB Least significant bit Most significant bit VA0 to VA3: Dot address in the vertical direction for the dot matrix character pattern VA0 LSB VA1 VA2 VA3 MSB Least significant bit Most significant bit No.7141-17/54 LC75810E/T 19 The figure below lists the correspondence between the data HA0 to HA2 which is dot address in the horizontal direction and the dot matrix character pattern, and the correspondence between the data VA0 to VA3 which is dot address in the vertical direction and the dot matrix character pattern. * 5-dot font width: 5 x 7, 5 x 8, or 5 x 9 dots Dot address in the horizontal direction HA0 to HA2 (HEX) 0 0 1 Dot address in VA0 to the vertical direction VA3 (HEX) 2 3 4 5 6 7 8 9 1 2 3 4 5 * The area at HA0 to 2 = 5H is allocated to the space at the right of the dot matrix character pattern. * The area at VA0 to 3 = 7H, for 5 x 7 dot characters, is allocated to the space at the bottom of the dot matrix character pattern. * The area at VA0 to 3 = 8H is illegal for 5 x 7 dot characters. For 5 x 8 dot characters, it is allocated to the space at the bottom of the dot matrix character pattern. * The area at VA0 to 3 = 9H is illegal for 5 x 7 or 5 x 8 dot characters. For 5 x 9 dot characters, it is allocated to the space at the bottom of the dot matrix character pattern. * 6-dot font width: 6 x 7, 6 x 8, or 6 x 9 dots Dot address in the horizontal direction HA0 to HA2 (HEX) 0 0 1 Dot address in the vertical direction VA0 to VA3 (HEX) 2 3 4 5 6 7 8 9 1 2 3 4 5 * The area at HA0 to 2 = 5H is allocated to the space at the right of the dot matrix character pattern. * The area at VA0 to 3 = 7H, for 6 x 7 dot characters, is allocated to the space at the bottom of the dot matrix character pattern. * The area at VA0 to 3 = 8H is illegal for 6 x 7 dot characters. For 6 x 8 dot characters, it is allocated to the space at the bottom of the dot matrix character pattern. * The area at VA0 to 3 = 9H is illegal for 6 x 7 or 6 x 8 dot characters. For 6 x 9 dot characters, it is allocated to the space at the bottom of the dot matrix character pattern. 20: Example of the "set AC and SC addresses" instruction execution Assume that a 32 digits x 2 lines display structure (OZ1 = 1, OZ2 = 0) has been set up with the "set display technique" instruction, and that the following data has been written to DCRAM with the "DCRAM data write" instruction. Display digit DCRAM data First line (DCRAM address (hexadecimal)) Second line (DCRAM address (hexadecimal)) Display digit DCRAM data First line (DCRAM address (hexadecimal)) Second line (DCRAM address (hexadecimal)) 1 A (00) 0 (20) 17 Q (10) g (30) 2 B (01) 1 (21) 18 R (11) h (31) 3 C (02) 2 (22) 19 S (12) i (32) 4 D (03) 3 (23) 20 T (13) j (33) 5 E (04) 4 (24) 21 U (14) k (34) 6 F (05) 5 (25) 22 V (15) l (35) 7 G (06) 6 (26) 23 W (16) m (36) 8 H (07) 7 (27) 24 X (17) n (37) 9 I (08) 8 (28) 25 Y (18) o (38) 10 J (09) 9 (29) 26 Z (19) p (39) 11 K (0A) a (2A) 27 < (1A) q (3A) 12 L (0B) b (2B) 28 > (1B) r (3B) 13 M (0C) c (2C) 29 z (1C) s (3C) 14 N (0D) d (2D) 30 y (1D) t (3D) 15 O (0E) e (2E) 31 x (1E) u (3E) 16 P (0F) f (2F) 32 w (1F) v (3F) No.7141-18/54 LC75810E/T * When DA0 to 5 is set to 07H, HA0 to 2 is set to 0H, and VA0 to 3 is set to 0H. HA0 0 HA1 0 HA2 0 VA0 0 VA1 0 VA2 0 VA3 0 DA0 1 DA1 1 DA2 1 DA3 0 DA4 0 DA5 0 (5 x 7 dot matrix) (6 x 7 dot matrix) * When DA0 to 5 is set to 09H, HA0 to 2 is set to 4H, and VA0 to 3 is set to 0H. HA0 0 HA1 0 HA2 1 VA0 0 VA1 0 VA2 0 VA3 0 DA0 1 DA1 0 DA2 0 DA3 1 DA4 0 DA5 0 (5 x 7 dot matrix) (6 x 7 dot matrix) * When DA0 to 5 is set to 0FH, HA0 to 2 is set to 0H, and VA0 to 3 is set to 3H. HA0 0 HA1 0 HA2 0 VA0 1 VA1 1 VA2 0 VA3 0 DA0 1 DA1 1 DA2 1 DA3 1 DA4 0 DA5 0 (5 x 7 dot matrix) (6 x 7 dot matrix) No.7141-19/54 LC75810E/T * When DA0 to 5 is set to 14H, HA0 to 2 is set to 1H, and VA0 to 3 is set to 2H. HA0 1 HA1 0 HA2 0 VA0 0 VA1 1 VA2 0 VA3 0 DA0 0 DA1 0 DA2 1 DA3 0 DA4 1 DA5 0 (5 x 7 dot matrix) (6 x 7 dot matrix) * When DA0 to 5 is set to 34H, HA0 to 2 is set to 3H, and VA0 to 3 is set to 6H. HA0 1 HA1 1 HA2 0 VA0 0 VA1 1 VA2 1 VA3 0 DA0 0 DA1 0 DA2 1 DA3 0 DA4 1 DA5 1 (5 x 7 dot matrix) (6 x 7 dot matrix) * DCRAM data write *** Code D120 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D 132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5 X X IM1 IM2 X 0 0 1 0 1 X: don't care DA0 to DA5: DCRAM address DA0 LSB DA1 DA2 DA3 DA4 DA5 MSB Least significant bit Most significant bit AC0 to AC7: DCRAM data (character code) AC0 LSB AC1 AC2 AC3 AC4 AC5 AC6 AC7 MSB Least significant bit Most significant bit This instruction writes the 8 bits of data AC0 to AC7 to DCRAM. This data is a character code, and is converted to a 5 x 7, 5 x 8, or 5 x 9 dot matrix display data using CGROM or CGRAM. No.7141-20/54 LC75810E/T IM1 and IM2: Sets the method of writing data to DCRAM IM1 0 1 0 IM2 0 0 1 * DCRAM data write method Normal DCRAM data write (Specifies the DCRAM address and writes the DCRAM data.) Normal increment mode DCRAM data write (Increments the DCRAM address by +1 each time data is written to DCRAM.) Super-increment mode DCRAM data write (Writes 2 to 16 characters of DCRAM data in a single operation.) 21 DCRAM data write method when IM1 is 0 and IM2 is 0. CE CCB address DI DCRAM Instruction execution time (27 s) Instruction execution time (27 s) DCRAM data write finishes Instruction execution time (27 s) DCRAM data write finishes Instruction execution time (27 s) (1) 24 bits CCB address (1) 24 bits CCB address (1) 24 bits CCB address (1) 24 bits DCRAM data write finishes DCRAM data write finishes * DCRAM data write method when IM1 is 1 and IM2 is 0. (Instructions other than the "DCRAM data write" instruction cannot be executed.) CE CCB address DI (2) 24 bits CCB address CCB address (3) 8 bits (3) 8 bits CCB address CCB address (3) 8 bits CCB address (3) 8 bits (4) 16 bits DCRAM Instruction execution time (27 s) DCRAM data write finishes Instruction execution time (27 s) Instruction execution time (27 s) DCRAM data write finishes Instruction execution time (27 s) Instruction execution time (27 s) Instruction execution time (27 s) DCRAM data write finishes DCRAM data write finishes DCRAM data write finishes DCRAM data write finishes (Instructions other than the "DCRAM data write" instruction cannot be executed.) * DCRAM data write method when IM1 is 0 and IM2 is 1. CE CCB address DI DCRAM Instruction execution time (ti s) Instruction execution time (ti s) Instruction execution time (ti s) (5) n bit CCB address (5) n bit CCB address (5) n bit DCRAM data write finishes DCRAM data write finishes DCRAM data write finishes n ti = 13.5s x ( -1) (n = 8m + 16, m is an integer between 2 and 16 that is the number of characters written as DCRAM 8 data.) For example When n = 32 bits (m = 2): ti = 40.5 s (when fosc = 300 kHz) When n = 80 bits (m = 8): ti = 121.5 s (when fosc = 300 kHz) When n = 144 bits (m = 16): ti = 229.5 s (when fosc = 300 kHz) Note that the instruction execution time of 27 s and ti values in s apply when fosc = 300 kHz, and that these times will differ when the oscillator frequency fosc differs. No.7141-21/54 LC75810E/T Data format (1) (24 bits) Code D120 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5 X X 0 0 X 0 0 1 0 1 X: don't care Data format (2) (24 bits) Code D120 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5 X X 1 0 X 0 0 1 0 1 X: don't care Data format (3) (8 bits) Code D136 AC0 D137 AC1 D138 AC2 D139 AC3 D140 AC4 D141 AC5 D142 AC6 D143 AC7 Data format (4) (16 bits) Code D128 AC0 D129 AC1 D130 AC2 D131 AC3 D132 AC4 D133 AC5 D134 AC6 D135 AC7 D136 D137 0 0 D138 X D139 D140 0 0 D141 1 D142 0 D143 1 X:don't care Data format (5) (n bits) Code Dz Dz+1 Dz+2 Dz+3 Dz+4 Dz+5 Dz+6 Dz+7 AC01 AC11 AC21 AC31 AC41 AC51 AC61 AC71 Code D112 D113 D114 D115 D116 D117 D118 D119 AC0m-1 AC1m-1 AC2m-1 AC3m-1 AC4m-1 AC5m-1 AC6m-1 AC7m-1 D120 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 AC0m AC1m AC2m AC3m AC4m AC5m AC6m AC7m DA01 DA11 DA21 DA31 DA41 DA51 X X 0 1 X 0 0 1 0 1 X: don't care Here, n = 8m + 16, z = 128 - 8m (m is an integer between 2 and 16 that is the number of characters written as DCRAM data.) Correspondence between the DCRAM address and the DCRAM data DCRAM address DA01 to DA51 (DA01 to DA51) + 1 (DA01 to DA51) + 2 DCRAM data AC01 to AC71 AC02 to AC72 AC03 to AC73 (DA01 to DA51) + (m - 3) (DA01 to DA51) + (m - 2) (DA01 to DA51) + (m - 1) AC0m-2 to AC7m-2 AC0m-1 to AC7m-1 AC0m to AC7m No.7141-22/54 LC75810E/T Example 1: When n = 32 bits (m = 2: 2 characters DCRAM data write operation) Code D112 AC01 D113 AC11 D114 AC21 D115 AC31 D116 AC41 D117 AC51 D118 AC61 D119 AC71 D120 AC02 D121 AC12 D122 AC22 D123 AC32 D124 AC42 D125 AC52 D126 AC62 D127 AC72 Code D128 DA01 D129 DA11 D130 DA21 D131 DA31 D132 DA41 D133 DA51 D134 X D135 X D136 0 D137 1 D138 X D139 0 D140 0 D141 1 D142 0 D143 1 X: don't care Correspondence between the DCRAM address and the DCRAM data DCRAM address DA01 to DA51 (DA01 to DA51) + 1 DCRAM data AC01 to AC71 AC02 to AC72 Example 2: When n = 80 bits (m = 8: 8 characters DCRAM data write operation) Code D64 AC01 D65 AC11 D66 AC21 D67 AC31 D68 AC41 D69 AC51 D70 AC61 D71 AC71 D72 AC02 D73 AC12 D74 AC22 D75 AC32 D76 AC42 D77 AC52 D78 AC62 D79 AC72 Code D80 AC03 D81 AC13 D82 AC23 D83 AC33 D84 AC43 D85 AC53 D86 AC63 D87 AC73 D88 AC04 D89 AC14 D90 AC24 D91 AC34 D92 AC44 D93 AC54 D94 AC64 D95 AC74 Code D96 AC05 D97 AC15 D98 AC25 D99 AC35 D100 AC45 D101 AC55 D102 AC65 D103 AC75 D104 AC06 D105 AC16 D106 AC26 D107 AC36 D108 AC46 D109 AC56 D110 AC66 D111 AC76 Code D112 AC07 D113 AC17 D114 AC27 D115 AC37 D116 AC47 D117 AC57 D118 AC67 D119 AC77 D120 AC08 D121 AC18 D122 AC28 D123 AC38 D124 AC48 D125 AC58 D126 AC68 D127 AC78 Code D128 DA01 D129 DA11 D130 DA21 D131 DA31 D132 DA41 D133 DA51 D134 X D135 X D136 0 D137 1 D138 X D139 0 D140 0 D141 1 D142 0 D143 1 X: don't care Correspondence between the DCRAM address and the DCRAM data DCRAM address DA01 to DA51 (DA01 to DA51) + 1 (DA01 to DA51) + 2 (DA01 to DA51) + 3 (DA01 to DA51) + 4 (DA01 to DA51) + 5 (DA01 to DA51) + 6 (DA01 to DA51) + 7 DCRAM data AC01 to AC71 AC02 to AC72 AC03 to AC73 AC04 to AC74 AC05 to AC75 AC06 to AC76 AC07 to AC77 AC08 to AC78 No.7141-23/54 LC75810E/T Example 3: When n = 144 bits (m = 16: 16 characters DCRAM data write operation) Code D0 AC00 D1 AC10 D2 AC20 D3 AC30 D4 AC40 D5 AC50 D6 AC60 D7 AC70 D8 AC01 D9 AC11 D10 AC21 D11 AC31 D12 AC41 D13 AC51 D14 AC61 D15 AC71 Code D16 AC03 D17 AC13 D18 AC23 D19 AC33 D20 AC43 D21 AC53 D22 AC63 D23 AC73 D24 AC04 D25 AC14 D26 AC24 D27 AC34 D28 AC44 D29 AC54 D30 AC64 D31 AC74 Code D32 AC05 D33 AC15 D34 AC25 D35 AC35 D36 AC45 D37 AC55 D38 AC65 D39 AC75 D40 AC06 D41 AC16 D42 AC26 D43 AC36 D44 AC46 D45 AC56 D46 AC66 D47 AC76 Code D48 AC07 D49 AC17 D50 AC27 D51 AC37 D52 AC47 D53 AC57 D54 AC67 D55 AC77 D56 AC08 D57 AC18 D58 AC28 D59 AC38 D60 AC48 D61 AC58 D62 AC68 D63 AC78 Code D64 AC09 D65 AC19 D66 AC29 D67 AC39 D68 AC49 D69 AC59 D70 AC69 D71 AC79 D72 D73 D74 D75 D76 D77 D78 D79 AC010 AC110 AC210 AC310 AC410 AC510 AC610 AC710 Code D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 AC011 AC111 AC211 AC311 AC411 AC511 AC611 AC711 AC012 AC112 AC212 AC312 AC412 AC512 AC612 AC712 Code D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 AC013 AC113 AC213 AC313 AC413 AC513 AC613 AC713 AC014 AC114 AC214 AC314 AC414 AC514 AC614 AC714 Code D112 D113 D114 D115 D116 D117 D118 D119 D120 D121 D122 D123 D124 D125 D126 D127 AC015 AC115 AC215 AC315 AC415 AC515 AC615 AC715 AC016 AC116 AC216 AC316 AC416 AC516 AC616 AC716 Code D128 DA01 D129 DA11 D130 DA21 D131 DA31 D132 DA41 D133 DA51 D134 X D135 X D136 0 D137 1 D138 X D139 0 D140 0 D141 1 D142 0 D143 1 X: don't care Correspondence between the DCRAM address and the DCRAM data DCRAM address DA01 to DA51 (DA01 to DA51) + 1 (DA01 to DA51) + 2 (DA01 to DA51) + 3 (DA01 to DA51) + 4 (DA01 to DA51) + 5 (DA01 to DA51) + 6 (DA01 to DA51) + 7 DCRAM data AC01 to AC71 AC02 to AC72 AC03 to AC73 AC04 to AC74 AC05 to AC75 AC06 to AC76 AC07 to AC77 AC08 to AC78 DCRAM address (DA01 to DA51) + 8 (DA01 to DA51) + 9 (DA01 to DA51) + 10 (DA01 to DA51) + 11 (DA01 to DA51) + 12 (DA01 to DA51) + 13 (DA01 to DA51) + 14 (DA01 to DA51) + 15 DCRAM data AC09 to AC79 AC010 to AC710 AC011 to AC711 AC012 to AC712 AC013 to AC713 AC014 to AC714 AC015 to AC715 AC016 to AC716 No.7141-24/54 LC75810E/T * ALATCH data write D56 AD1 D57 AD2 D58 AD3 ***** Code D60 AD5 D61 AD6 D62 AD7 D63 AD8 D64 AD9 D65 D66 D67 D68 D69 D70 D71 D59 AD4 AD10 AD11 AD12 AD13 AD14 AD15 AD16 Code D72 AD17 D73 AD18 D74 AD19 D75 AD20 D76 AD21 D77 AD22 D78 AD23 D79 AD24 D80 D81 D82 D83 D84 D85 D86 D87 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AD32 Code D88 AD33 D89 AD34 D90 AD35 D91 AD36 D92 AD37 D93 AD38 D94 AD39 D95 AD40 D96 D97 D98 D99 D100 D101 D102 D103 AD41 AD42 AD43 AD44 AD45 AD46 AD47 AD48 Code D104 AD49 D105 AD50 D106 AD51 D107 AD52 D108 AD53 D109 AD54 D110 AD55 D111 AD56 D112 D113 D114 D115 D116 D117 D118 D119 AD57 AD58 AD59 AD60 AD61 AD62 AD63 AD64 Code D120 AD65 D121 AD66 D122 AD67 D123 AD68 D124 AD69 D125 AD70 D126 AD71 D127 AD72 D128 D129 D130 D131 D132 D133 D134 D135 AD73 AD74 AD75 AD76 AD77 AD78 AD79 AD80 Code D136 X D137 X D138 X D139 0 D140 0 D141 1 D142 1 D143 0 X: don't care AD1 to AD80: ADATA display data In addition to the 5 x 7, 5 x 8, 5 x 9, 6 x 7, 6 x 8, or 6 x 9 dot matrix display data (MDATA), the LC75810E/T also supports an accessory display of 5 or 6 segments (ADATA) at each display digit, and allows arbitrary data to be displayed directly without going through CGROM or CGRAM. The figure below shows the correspondence between that data and the display. When ADn = 1 (where n is an integer between 1 and 80), the segment corresponding to that data will be turned on. 5-dot font width (5 x 7, 5 x 8, or 5 x 9 dots) COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 S80/COM9 S79/COM10 S76 S77 S78 COM10/S79 COM9/S80 No.7141-25/54 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD71 AD72 AD73 AD74 AD75 AD76 AD77 AD78 AD79 AD80 S6 S7 S8 S9 S10 S71 S72 S73 S74 S75 S1 S2 S3 S4 S5 LC75810E/T 6-dot font width (6 x 7, 6 x 8, or 6 x 9 dots) COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 S80/COM9 S79/COM10 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 ADATA AD61 AD62 AD63 AD64 AD65 AD66 AD67 AD68 AD69 AD70 AD71 AD72 AD73 AD74 AD75 AD76 AD77 AD78 AD79 AD80 Corresponding output pin S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD67 AD68 AD69 AD70 AD71 AD72 AD73 AD74 AD75 AD76 AD77 AD78 Correspondence between ADATA and the output pins ADATA AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 Corresponding output pin S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 ADATA AD31 AD32 AD33 AD34 AD35 AD36 AD37 AD38 AD39 AD40 AD41 AD42 AD43 AD44 AD45 AD46 AD47 AD48 AD49 AD50 AD51 AD52 AD53 AD54 AD55 AD56 AD57 AD58 AD59 AD60 Corresponding output pin No.7141-26/54 LC75810E/T * CGRAM data write D80 CD1 D81 CD2 D82 CD3 ***** Code D84 CD5 D85 CD6 D86 CD7 D87 CD8 D88 CD9 D89 D90 D91 D92 D93 D94 D95 D83 CD4 CD10 CD11 CD12 CD13 CD14 CD15 CD16 Code D96 CD17 D97 CD18 D98 CD19 D99 CD20 D100 CD21 D101 CD22 D102 CD23 D103 D104 D105 D106 D107 D108 D109 D110 D111 CD24 CD25 CD26 CD27 CD28 CD29 CD30 CD31 CD32 Code D112 CD33 D113 CD34 D114 CD35 D115 CD36 D116 CD37 D117 CD38 D118 CD39 D119 D120 D121 D122 D123 D124 D125 X D126 X D127 X CD40 CD41 CD42 CD43 CD44 CD45 Code D128 CA0 D129 CA1 D130 CA2 D131 CA3 D132 CA4 D133 CA5 D134 CA6 D135 CA7 D136 WM D137 X D138 X D139 0 D140 0 D141 1 D142 1 D143 1 X:don't care CA0 to CA7: CGRAM address CA0 LSB CA1 CA2 CA3 CA4 CA5 CA6 CA7 MSB Least significant bit Most significant bit CD1 to CD45: CGRAM data (5 x 7, 5 x 8, or 5 x 9 dot matrix display data) The bit CDn (where n is an integer between 1 and 45) corresponds to the 5 x 7, 5 x 8, or 5 x 9 dot matrix display data. The figure below shows that correspondence. When CDn is 1, the dots which correspond to that data will be turned on. CD1 CD6 CD11 CD16 CD21 CD26 CD31 CD36 CD41 CD2 CD7 CD12 CD17 CD22 CD27 CD32 CD37 CD42 CD3 CD8 CD13 CD18 CD23 CD28 CD33 CD38 CD43 CD4 CD9 CD14 CD19 CD24 CD29 CD34 CD39 CD44 CD5 CD10 CD15 CD20 CD25 CD30 CD35 CD40 CD45 *22: CD1 to CD35: 5 x 7 dot matrix display data CD1 to CD40: 5 x 8 dot matrix display data CD1 to CD45: 5 x 9 dot matrix display data No.7141-27/54 LC75810E/T WM: Sets the method of writing data to CGRAM. WM 0 1 CGRAM data write method Normal CGRAM data write (Specifies a CGRAM address and write a CGRAM data.) Double write mode CGRAM data write (Specifies two CGRAM addresses and writes two CGRAM data to those addresses.) * 23: CGRAM data write method when WM is 0. CE CCB address DI (6) 64 bits CCB address (6) 64 bits CCB address (6) 64 bits CCB address (6) 64 bits CGRAM Instruction execution time (27 s) Instruction execution time (27 s) CGRAM data write finishes Instruction execution time (27 s) CGRAM data write finishes Instruction execution time (27 s) CGRAM data write finishes CGRAM data write finishes * CGRAM data write method when WM is 1. CE CCB address DI (7) 120 bits CCB address (7) 120 bits CCB address (7) 120 bits CGRAM Instruction execution time (40.5s) Instruction execution time (40.5s) Instruction execution time (40.5s) CGRAM data write finishes CGRAM data write finishes CGRAM data write finishes Note that the instruction execution times of 27 s and 40.5 s apply when fosc = 300 kHz, and that these times will differ when the oscillator frequency fosc differs. Data format (6) (64 bits) Code D80 CD1 D81 CD2 D82 CD3 D83 CD4 D84 CD5 D85 CD6 D86 CD7 D87 CD8 D88 CD9 D89 D90 D91 D92 D93 D94 D95 CD10 CD11 CD12 CD13 CD14 CD15 CD16 Code D96 CD17 D97 CD18 D98 CD19 D99 CD20 D100 CD21 D101 CD22 D102 CD23 D103 D104 D105 D106 D107 D108 D109 D110 D111 CD24 CD25 CD26 CD27 CD28 CD29 CD30 CD31 CD32 Code D112 CD33 D113 CD34 D114 CD35 D115 CD36 D116 CD37 D117 CD38 D118 CD39 D119 D120 D121 D122 D123 D124 D125 X D126 X D127 X CD40 CD41 CD42 CD43 CD44 CD45 Code D128 CA0 D129 CA1 D130 CA2 D131 CA3 D132 CA4 D133 CA5 D134 CA6 D135 CA7 D136 0 D137 X D138 X D139 0 D140 0 D141 1 D142 1 D143 1 X: don't care No.7141-28/54 LC75810E/T Data format (7) (120 bits) Code D24 CD11 D25 CD21 D26 CD31 D27 CD41 D28 CD51 D29 CD61 D30 CD71 D31 CD81 D32 CD91 D33 D34 D35 D36 D37 D38 D39 CD101 CD111 CD121 CD131 CD141 CD151 CD161 Code D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 CD171 CD181 CD191 CD201 CD211 CD221 CD231 CD241 CD251 CD261 CD271 CD281 CD291 CD301 CD311 CD321 Code D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 X D70 X D71 X CD331 CD341 CD351 CD361 CD371 CD381 CD391 CD401 CD411 CD421 CD431 CD441 CD451 Code D72 CA01 D73 CA11 D74 CA21 D75 CA31 D76 CA41 D77 CA51 D78 CA61 D79 CA71 D80 CD12 D81 CD22 D82 CD32 D83 CD42 D84 CD52 D85 CD62 D86 CD72 D87 CD82 Code D88 CD92 D89 D90 D91 D92 D93 D94 D95 D96 D97 D98 D99 D100 D101 D102 D103 CD102 CD112 CD122 CD132 CD142 CD152 CD162 CD172 CD182 CD192 CD202 CD212 CD222 CD232 CD242 Code D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 CD252 CD262 CD272 CD282 CD292 CD302 CD312 CD322 CD332 CD342 CD352 CD362 CD372 CD382 CD392 CD402 Code D120 D121 D122 D123 D124 D125 X D126 X D127 X D128 CA02 D129 CA12 D130 CA22 D131 CA32 D132 CA42 D133 CA52 D134 CA62 D135 CA72 CD412 CD422 CD432 CD442 CD452 Code D136 1 D137 X D138 X D139 0 D140 0 D141 1 D142 1 D143 1 X: don't care Correspondence between the CGRAM address and the CGRAM data CGRAM address CA01 to CA71 CA02 to CA72 CGRAM data CD11 to CD451 CD12 to CD452 No.7141-29/54 LC75810E/T * Set display contrast D128 CT0 D129 CT1 D130 CT2 ***** Code D132 X D133 X D134 X D135 X D136 CTC D137 X D138 X D139 0 D140 1 D141 0 D142 0 D143 0 D131 CT3 X:don't care CT0 to CT3: Sets the display contrast (11 steps) CT0 0 1 0 1 0 1 0 1 0 1 0 CT1 0 0 1 1 0 0 1 1 0 0 1 CT2 0 0 0 0 1 1 1 1 0 0 0 CT3 0 0 0 0 0 0 0 0 1 1 1 LCD drive 4/4 bias voltage supply VLCD0 level 0.94VLCD = VLCD-(0.03VLCD x 2) 0.91VLCD = VLCD-(0.03VLCD x 3) 0.88VLCD = VLCD-(0.03VLCD x 4) 0.85VLCD = VLCD-(0.03VLCD x 5) 0.82VLCD = VLCD-(0.03VLCD x 6) 0.79VLCD = VLCD-(0.03VLCD x 7) 0.76VLCD = VLCD-(0.03VLCD x 8) 0.73VLCD = VLCD-(0.03VLCD x 9) 0.70VLCD = VLCD-(0.03VLCD x 10) 0.67VLCD = VLCD-(0.03VLCD x 11) 0.64VLCD = VLCD-(0.03VLCD x 12) CTC: Sets the display contrast adjustment circuit state CTC 0 1 Display contrast adjustment circuit state The display contrast adjustment circuit is disabled, and the VLCD0 pin level is forced to the VLCD level. The display contrast adjustment circuit operates, and the display contrast is adjusted. Note that although the display contrast can be adjusted by operating the built-in display contrast adjustment circuit, it is also possible to be adjusted by varying the voltage level on the LCD driver block power supply VLCD pin. However, the level on VLCD0 must be greater than or equal to 4.5V. No.7141-30/54 LC75810E/T Notes on the Power On and Power Off Sequences The following sequences must be observed when power is turned on and off. (See Figure 3.) * At power on: Logic block power supply (VDD) on LCD driver block power supply (VLCD) on. * At power off: LCD driver block power supply (VLCD) off Logic block power supply (VDD) off. However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and off at the same time. t1 VDD t2 VLCD tWRES RES VIL VIH Instruction execution Initial state settings Display state Display off Display on t3 Display off "Display on/off control" instruction execution (Turning the display on) Initial state setting * Set display technique * t1 0 * t2 > 0 * t3 0 (t2 > t3) * tWRES * * * "Display on/off control" instruction execution (Turning the display off) * DCRAM data write * ALATCH data write (If ALATCH is used) * CGRAM data write (If CGRAM is used) * Set AC and SC addresses * Set display contrast (If the display contrast adjustment circuit is used) 1s min Figure 3 No.7141-31/54 LC75810E/T 1/8 Duty, 1/4 Bias Drive Technique VLCD0 VLCD1 COM1 VLCD2 VLCD3 VSS VLCD0 VLCD1 COM2 VLCD2 VLCD3 VSS VLCD0 VLCD1 COM8 VLCD2 VLCD3 VSS VLCD0 VLCD1 VLCD2 VLCD3 VSS VLCD0 LCD driver output when only LCD segments corresponding to COM1 are turned on VLCD1 VLCD2 VLCD3 VSS VLCD0 LCD driver output when only LCD segments corresponding to COM2 are turned on VLCD1 VLCD2 VLCD3 VSS VLCD0 LCD driver output when all LCD segments corresponding to COM1 to COM8 are turned on VLCD1 VLCD2 VLCD3 VSS LCD driver output when all LCD segments corresponding to COM1 to COM8 are turned off T8 8 T8 1 f8 fosc 3072 fosc 1536 T8 = When a "set display technique" instruction with FC = 0 is executed: f8 = When a "set display technique" instruction with FC = 1 is executed: f8 = No.7141-32/54 LC75810E/T 1/9 Duty, 1/4 Bias Drive Technique VLCD0 VLCD1 COM1 VLCD2 VLCD3 VSS VLCD0 VLCD1 COM2 VLCD2 VLCD3 VSS VLCD0 VLCD1 COM9 VLCD2 VLCD3 VSS VLCD0 VLCD1 VLCD2 VLCD3 VSS VLCD0 LCD driver output when only LCD segments corresponding to COM1 are turned on VLCD1 VLCD2 VLCD3 VSS VLCD0 LCD driver output when only LCD segments corresponding to COM2 are turned on VLCD1 VLCD2 VLCD3 VSS VLCD0 LCD driver output when all LCD segments corresponding to COM1 to COM9 are turned on VLCD1 VLCD2 VLCD3 VSS LCD driver output when all LCD segments corresponding to COM1 to COM9 are turned off T9 9 T9 1 f9 fosc 3456 fosc 1728 T9= When a "set display technique" instruction with FC = 0 is executed: f9 = When a "set display technique" instruction with FC = 1 is executed: f9 = No.7141-33/54 LC75810E/T 1/10 Duty, 1/4 Bias Drive Technique VLCD0 VLCD1 COM1 VLCD2 VLCD3 VSS VLCD0 VLCD1 COM2 VLCD2 VLCD3 VSS VLCD0 VLCD1 COM10 VLCD2 VLCD3 VSS VLCD0 LCD driver output when all LCD segments corresponding to COM1 to COM10 are turned off VLCD1 VLCD2 VLCD3 VSS VLCD0 LCD driver output when only LCD segments corresponding to COM1 are turned on VLCD1 VLCD2 VLCD3 VSS VLCD0 LCD driver output when only LCD segments corresponding to COM2 are turned on VLCD1 VLCD2 VLCD3 VSS VLCD0 LCD driver output when all LCD segments corresponding to COM1 to COM10 are turned on VLCD1 VLCD2 VLCD3 VSS T10 10 T10 T10 = 1 f10 fosc 3840 fosc 1920 When a "set display technique" instruction with FC = 0 is executed: f10 = When a "set display technique" instruction with FC = 1 is executed: f10 = No.7141-34/54 LC75810E/T Sample Application Circuit 1 5 x 7 dot matrix, 1/8 duty, 1/4 bias drive (for use with normal panels) LCD panel +5 V VDD VSS COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S76 S77 S78 COM10/S79 COM9/S80 +8 V OPEN VLCD VLCD0 VLCD1 VLCD2 VLCD3 C C 0.047 F C C OSC From the controller RES CE CL DI Sample Application Circuit 2 5 x 7 dot matrix, 1/8 duty, 1/4 bias drive (for use with large panels) LCD panel +5 V VDD VSS COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S76 S77 S78 COM10/S79 COM9/S80 +8 V VLCD R R R C C C R OSC VLCD2 VLCD3 VLCD0 VLCD1 C 0.047 F 10 k R 2.2 k From the controller RES CE CL DI No.7141-35/54 LC75810E/T Sample Application Circuit 3 5 x 8 dot matrix, 1/9 duty, 1/4 bias drive (for use with normal panels) LCD panel +5 V VDD VSS COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 S80/COM9 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S76 S77 S78 COM10/S79 +8 V OPEN VLCD VLCD0 VLCD1 VLCD2 C C C VLCD3 C 0.047 F OSC From the controller RES CE CL DI Sample Application Circuit 4 5 x 8 dot matrix, 1/9 duty, 1/4 bias drive (for use with large panels) LCD panel +5 V VDD VSS COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 S80/COM9 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S76 S77 S78 COM10/S79 +8 V VLCD R R VLCD2 R VLCD0 VLCD1 VLCD3 C C 0.047 F 10 k R 2.2 k C C R OSC From the controller RES CE CL DI No.7141-36/54 LC75810E/T Sample Application Circuit 5 5 x 9 dot matrix, 1/10 duty, 1/4 bias drive (for use with normal panels) LCD panel +5 V VDD VSS COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 S80/COM9 S79/COM10 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S76 S77 S78 +8 V OPEN VLCD VLCD0 VLCD1 VLCD2 C C C VLCD3 C 0.047 F OSC From the controller RES CE CL DI Sample Application Circuit 6 5 x 9 dot matrix, 1/10 duty, 1/4 bias drive (for use with large panels) LCD panel +5 V VDD VSS COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 S80/COM9 S79/COM10 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S76 S77 S78 +8 V VLCD R R R C C C R OSC VLCD2 VLCD3 VLCD0 VLCD1 C 0.047 F 10 k R 2.2 k From the controller RES CE CL DI No.7141-37/54 LC75810E/T Sample Application Circuit 7 6 x 7 dot matrix, 1/8 duty, 1/4 bias drive (for use with normal panels) LCD panel +5 V VDD VSS COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S73 S74 S75 S76 S77 S78 COM10/S79 COM9/S80 +8 V OPEN VLCD VLCD0 VLCD1 VLCD2 C C C VLCD3 C 0.047 F OSC From the controller RES CE CL DI OPEN Sample Application Circuit 8 6 x 7 dot matrix, 1/8 duty, 1/4 bias drive (for use with large panels) LCD panel +5 V VDD VSS COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S73 S74 S75 S76 S77 S78 COM10/S79 COM9/S80 +8 V VLCD R R R C C C R OSC VLCD2 VLCD3 VLCD0 VLCD1 C 0.047 F 10 k R 2.2 k From the controller RES CE CL DI OPEN No.7141-38/54 LC75810E/T Sample Application Circuit 9 6 x 8 dot matrix, 1/9 duty, 1/4 bias drive (for use with normal panels) LCD panel +5 V VDD VSS COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 S80/COM9 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S73 S74 S75 S76 S77 S78 COM10/S79 +8 V OPEN VLCD VLCD0 VLCD1 VLCD2 C C C VLCD3 C 0.047 F OSC From the controller RES CE CL DI OPEN Sample Application Circuit 10 6 x 8 dot matrix, 1/9 duty, 1/4 bias drive (for use with large panels) LCD panel +5 V VDD VSS COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 S80/COM9 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S73 S74 S75 S76 S77 S78 COM10/S79 +8 V VLCD R R R C C C R OSC VLCD2 VLCD3 VLCD0 VLCD1 C 0.047 F 10 k R 2.2 k From the controller RES CE CL DI OPEN No.7141-39/54 LC75810E/T Sample Application Circuit 11 6 x 9 dot matrix, 1/10 duty, 1/4 bias drive (for use with normal panels) LCD panel +5 V VDD VSS COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 S80/COM9 S79/COM10 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S73 S74 S75 S76 S77 S78 +8 V OPEN VLCD VLCD0 VLCD1 VLCD2 C C C VLCD3 C 0.047F OSC From the controller RES CE CL DI Sample Application Circuit 12 6 x 9 dot matrix, 1/10 duty, 1/4 bias drive (for use with large panels) LCD panel +5 V VDD VSS COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 S80/COM9 S79/COM10 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S73 S74 S75 S76 S77 S78 +8 V VLCD R R R C C C R OSC VLCD2 VLCD3 VLCD0 VLCD1 C 0.047 F 10 k R 2.2 k From the controller RES CE CL DI No.7141-40/54 Sample 1 showing the Correspondence between Instructions and the Display (Using the LC75810-8725 with a 5 x 7 dots, 16 digits x 1 line display) MSB No. LSB Instruction (hexadecimal) Display Initializes the IC. The display is in the off state. Operation D112 to D115 D116 to D119 D120 to D123 D124 to D127 D128 to D131 D132 to D135 D136 to D139 D140 to D143 1 Power application (initialization with the RES pin) 2 0 0 8 Set display technique 1 Sets to the 1/8 duty 1/4 bias display technique, the 32 digits x 2 lines display structure, and the 5-dot font width at each digit. Writes the display data "S" to DCRAM address 00H. 3 0 1 A DCRAM data write (normal increment mode) 3 5 0 4 1 4 DCRAM data write (normal increment mode) Writes the display data "A" to DCRAM address 01H. 5 E 4 DCRAM data write (normal increment mode) Writes the display data "N" to DCRAM address 02H. 6 9 5 DCRAM data write (normal increment mode) Writes the display data "Y" to DCRAM address 03H. 7 F 4 DCRAM data write (normal increment mode) Writes the display data "O" to DCRAM address 04H. 8 0 2 DCRAM data write (normal increment mode) Writes the display data " " to DCRAM address 05H. LC75810E/T 9 9 4 DCRAM data write (normal increment mode) Writes the display data "I" to DCRAM address 06H. 10 3 4 DCRAM data write (normal increment mode) Writes the display data "C" to DCRAM address 07H. 11 0 2 DCRAM data write (normal increment mode) Writes the display data " " to DCRAM address 08H. 12 C 4 DCRAM data write (normal increment mode) Writes the display data "L" to DCRAM address 09H. 13 3 4 DCRAM data write (normal increment mode) Writes the display data "C" to DCRAM address 0AH. 14 7 3 DCRAM data write (normal increment mode) Writes the display data "7" to DCRAM address 0BH. 15 5 3 DCRAM data write (normal increment mode) Writes the display data "5" to DCRAM address 0CH. 16 8 3 DCRAM data write (normal increment mode) Writes the display data "8" to DCRAM address 0DH. 17 1 3 DCRAM data write (normal increment mode) Writes the display data "1" to DCRAM address 0EH. Continued on next page. No.7141-41/54 Continued from perceding page. MSB No. LSB Instruction (hexadecunal) Display Operation Writes the display data "0" to DCRAM address 0FH. D112 to D115 D116 to D119 D120 to D123 D124 to D127 D128 to D131 D132 to D135 D136 to D139 D140 to D143 18 0 3 DCRAM data write (normal increment mode) 19 0 2 DCRAM data write (normal increment mode) Writes the display data " " to DCRAM address 10H. 20 C 4 DCRAM data write (normal increment mode) Writes the display data "L" to DCRAM address 11H. 21 3 4 DCRAM data write (normal increment mode) Writes the display data "C" to DCRAM address 12H. 22 4 4 DCRAM data write (normal increment mode) Writes the display data "D" to DCRAM address 13H. 23 0 2 DCRAM data write (normal increment mode) Writes the display data " " to DCRAM address 14H. 24 4 4 DCRAM data write (normal increment mode) Writes the display data "D" to DCRAM address 15H. 25 2 5 DCRAM data write (normal increment mode) Writes the display data "R" to DCRAM address 16H. LC75810E/T 26 9 4 DCRAM data write (normal increment mode) Writes the display data "I" to DCRAM address 17H. 27 6 5 DCRAM data write (normal increment mode) Writes the display data "V" to DCRAM address 18H. 28 5 4 DCRAM data write (normal increment mode) Writes the display data "E" to DCRAM address 19H. 29 2 5 DCRAM data write (normal increment mode) Writes the display data "R" to DCRAM address 1AH. 30 0 2 DCRAM data write (normal increment mode) Writes the display data " " to DCRAM address 1BH. 31 0 2 DCRAM data write (normal increment mode) Writes the display data " " to DCRAM address 1CH. 32 0 2 DCRAM data write (normal increment mode) Writes the display data " " to DCRAM address 1DH. 33 0 2 DCRAM data write (normal increment mode) Writes the display data " " to DCRAM address 1EH. 34 0 2 DCRAM data write (normal increment mode) Writes the display data " " to DCRAM address 1FH. Continued on next page. No.7141-42/54 Continued from preceding page. MSB No. LSB Instruction (hexadecimal) Display Writes the display data "D" to DCRAM address 20H. Operation D112 to D115 D116 to D119 D120 to D123 D124 to D127 D128 to D131 D132 to D135 D136 to D139 D140 to D143 35 4 4 DCRAM data write (normal increment mode) 36 F 4 DCRAM data write (normal increment mode) Writes the display data "O" to DCRAM address 21H. 37 4 5 DCRAM data write (normal increment mode) Writes the display data "T" to DCRAM address 22H. 38 0 2 DCRAM data write (normal increment mode) Writes the display data " " to DCRAM address 23H. 39 D 4 DCRAM data write (normal increment mode) Writes the display data "M" to DCRAM address 24H. 40 1 4 DCRAM data write (normal increment mode) Writes the display data "A" to DCRAM address 25H. 41 4 5 DCRAM data write (normal increment mode) Writes the display data "T" to DCRAM address 26H. 42 2 5 DCRAM data write (normal increment mode) Writes the display data "R" to DCRAM address 27H. LC75810E/T 43 9 4 DCRAM data write (normal increment mode) Writes the display data "I" to DCRAM address 28H. 44 8 5 DCRAM data write (normal increment mode) Writes the display data "X" to DCRAM address 29H. 45 0 2 DCRAM data write (normal increment mode) Writes the display data " " to DCRAM address 2AH. 46 4 5 DCRAM data write (normal increment mode) Writes the display data "T" to DCRAM address 2BH. 47 9 5 DCRAM data write (normal increment mode) Writes the display data "Y" to DCRAM address 2CH. 48 0 5 DCRAM data write (normal increment mode) Writes the display data "P" to DCRAM address 2DH. 49 5 4 DCRAM data write (normal increment mode) Writes the display data "E" to DCRAM address 2EH. 50 0 A DCRAM data write (normal increment mode) 0 2 Writes the display data " " to DCRAM address 2FH. 51 0 2 Set AC and SC addresses 0 0 0 0 0 0 Sets AC to the DCRAM address 00H, SC to the horizontal dot address 0H and the vertical dot address 0H. Continued on next page. No.7141-43/54 Continued from preceding page MSB No. LSB Instruction (hexadecimal) Display Turns on the LCD for all digits (16 digits) in MDATA. Operation D112 to D115 D116 to D119 D120 to D123 D124 to D127 D128 to D131 D132 to D135 D136 to D139 D140 to D143 52 1 4 Display on/off control F F F F 53 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 54 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 55 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 56 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 57 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 58 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 59 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. LC75810E/T 60 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 61 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 62 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 63 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 64 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 65 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 66 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 67 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 68 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. Continued on next page. No.7141-44/54 Continued from preceding page. MSB No. LSB Instruction (hexadecimal) Display Shifts just the MDATA display three dots to the left. Operation D112 to D115 D116 to D119 D120 to D123 D124 to D127 D128 to D131 D132 to D135 D136 to D139 D140 to D143 69 0 C Display scroll 3 0 0 0 70 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 71 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 72 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 73 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 74 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 75 0 2 Set AC and SC addresses 0 0 0 0 0 0 Sets AC to the DCRAM address 00H, SC to the horizontal dot address 0H and the vertical dot address 0H. Shifts just the MDATA display two dots to the up. 76 0 C Display scroll 0 0 2 0 LC75810E/T 77 0 C Display scroll 0 0 2 0 Shifts just the MDATA display two dots to the up. 78 0 C Display scroll 0 0 2 0 Shifts just the MDATA display two dots to the up. 79 0 C Display scroll 0 0 2 0 Shifts just the MDATA display two dots to the up. 80 8 4 Display on/off control 0 0 0 0 Sets to power saving mode, turns off the LCD for all digits. Turns on the LCD for all digits (16 digits) in MDATA. 81 1 4 Display on/off control F F F F 82 0 2 Set AC and SC addresses 0 0 0 0 0 0 Sets AC to the DCRAM address 00H, SC to the horizontal dot address 0H and the vertical dot address 0H. No.7141-45/54 Notes 24: In sample 1 showing the correspondence between instructions and the display, a 16 digits x 1 line 5 x 7 dot matrix LCD is used, and CGRAM and ALATCH are not used. 25: The data format will have the following format if super-increment mode is used for the "DCRAM data write" instructions (numbers 3 to 50) in sample 1 showing the correspondence between instructions and the display. Note that the sample below shows 48 characters of DCRAM data being divided into 3 separate "DCRAM data write" instruction executions in the super-increment mode. No. DCRAM data write (super-increment mode) E DCRAM data write (super-increment mode) 3 DCRAM data write (super-increment mode) 4 5 0 2 D 4 1 4 4 5 2 5 9 4 8 5 4 4 4 0 2 4 4 2 5 9 4 6 5 5 4 4 9 5 F 4 0 2 9 4 3 4 0 2 C 4 LSB Instruction MSB D 0 t o D 3 D 4 t o D 7 D8 to D11 D12 to D15 D16 to D19 D20 to D23 D24 to D27 D28 to D31 D32 to D35 D36 to D39 D40 to D43 D44 to D47 D48 to D51 D52 to D55 D56 to D59 D60 to D63 D64 to D67 D68 to D71 D72 to D75 D76 to D79 D80 to D83 D84 to D87 3 to 18 3 5 1 4 3 4 19 to 34 0 2 C 4 2 5 35 to 50 4 4 F 4 0 2 No. DCRAM data write (super-increment mode) 8 DCRAM data write (super-increment mode) 0 DCRAM data write (super-increment mode) 0 5 5 4 0 2 0 2 2 A 2 0 2 0 2 0 1 2 A 3 1 3 0 3 0 0 2 A LSB Instruction MSB D88 to D91 D92 to D95 D96 to D99 D100 to D103 D104 to D107 D108 to D111 D112 to D115 D116 to D119 D120 to D123 D124 to D127 D128 to D131 D132 to D135 D136 to D139 D140 to D143 Display Writes the display data "S" "A" "N" "Y" "O" " " "I" "C" " " "L" "C" "7" "5" "8" "1" "0" to DCRAM addresses 00H to 0FH. Writes the display data " " "L" "C" "D" " " "D" "R" "I" "V" "E" "R" " " " " " " " " " " to DCRAM addresses 10H to 1FH. Writes the display data "D" "O" "T" " " "M" "A" "T" "R" "I" "X" " " "T" "Y" "P" "E" " " to DCRAM addresses 20H to 2FH. 3 to 18 7 3 5 3 LC75810E/T 19 to 34 0 2 0 2 35 to 50 4 5 9 5 No.7141-46/54 Sample 2 showing the Correspondence between Instructions and the Display (Using the LC75810-8725 with a 6 x 7 dots, 13 digits x 1 line display) MSB Display Operation No LSB Instruction (hexadecimal) D112 to D115 D116 to D119 D120 to D123 D124 to D127 D128 to D131 D132 to D135 D136 to D139 D140 to D143 1 Power application (initialization with the RES pin) Initializes the IC. The display is in the off state. 2 0 0 8 Set display technique 5 Sets to the 1/8 duty 1/4 bias display technique, the 32 digits x 2 lines display structure, and the 6-dot font width at each digit. Writes the display data "S" to DCRAM address 00H. 3 0 1 A DCRAM data write (normal increment mode) 3 5 0 4 1 4 DCRAM data write (normal increment mode) Writes the display data "A" to DCRAM address 01H. 5 E 4 DCRAM data write (normal increment mode) Writes the display data "N" to DCRAM address 02H. 6 9 5 DCRAM data write (normal increment mode) Writes the display data "Y" to DCRAM address 03H. 7 F 4 DCRAM data write (normal increment mode) Writes the display data "O" to DCRAM address 04H. 8 0 2 DCRAM data write (normal increment mode) Writes the display data " " to DCRAM address 05H. LC75810E/T 9 C 4 DCRAM data write (normal increment mode) Writes the display data "L" to DCRAM address 06H. 10 3 4 DCRAM data write (normal increment mode) Writes the display data "C" to DCRAM address 07H. 11 7 3 DCRAM data write (normal increment mode) Writes the display data "7" to DCRAM address 08H. 12 5 3 DCRAM data write (normal increment mode) Writes the display data "5" to DCRAM address 09H. 13 8 3 DCRAM data write (normal increment mode) Writes the display data "8" to DCRAM address 0AH. 14 1 3 DCRAM data write (normal increment mode) Writes the display data "1" to DCRAM address 0BH. 15 0 3 DCRAM data write (normal increment mode) Writes the display data "0" to DCRAM address 0CH. 16 0 2 DCRAM data write (normal increment mode) Writes the display data " " to DCRAM address 0DH. 17 C 4 DCRAM data write (normal increment mode) Writes the display data "L" to DCRAM address 0EH. Continued on next page. No.7141-47/54 Continued from preceding page. No. LSB Instruction (hexadecimal) MSB Display Writes the display data "C" to DCRAM address 0FH. Operation D112 to D115 D116 to D119 D120 to D123 D124 to D127 D128 to D131 D132 to D135 D136 to D139 D140 to D143 18 3 Writes the display data "D" to DCRAM address 10H. 4 DCRAM data write (normal increment mode) 19 4 Writes the display data " " to DCRAM address 11H. 4 DCRAM data write (normal increment mode) 20 0 2 DCRAM data write (normal increment mode) 21 4 4 DCRAM data write (normal increment mode) Writes the display data "D" to DCRAM address 12H. 22 2 5 DCRAM data write (normal increment mode) Writes the display data "R" to DCRAM address 13H. 23 9 4 DCRAM data write (normal increment mode) Writes the display data "I" to DCRAM address 14H. 24 6 5 DCRAM data write (normal increment mode) Writes the display data "V" to DCRAM address 15H. 25 5 4 DCRAM data write (normal increment mode) Writes the display data "E" to DCRAM address 16H. 26 2 5 LC75810E/T DCRAM data write (normal increment mode) Writes the display data "R" to DCRAM address 17H. 27 0 2 DCRAM data write (normal increment mode) Writes the display data " " to DCRAM address 18H. 28 2 0 A DCRAM data write (normal increment mode) Writes the display data " " to DCRAM address 19H. 0 29 2 1 A DCRAM data write (normal increment mode) Writes the display data "D" to DCRAM address 20H. 4 4 0 30 F 4 DCRAM data write (normal increment mode) Writes the display data "O" to DCRAM address 21H. 31 4 5 DCRAM data write (normal increment mode) Writes the display data "T" to DCRAM address 22H. 32 0 2 DCRAM data write (normal increment mode) Writes the display data " " to DCRAM address 23H. 33 D 4 DCRAM data write (normal increment mode) Writes the display data "M" to DCRAM address 24H. 34 1 4 DCRAM data write (normal increment mode) Writes the display data "A" to DCRAM address 25H. Continued on next page. No.7141-48/54 Continued from preceding page. MSB No. LSB Instruction (hexadecimal) Display Writes the display data "T" to DCRAM address 26H. Operation D112 to D115 D116 to D119 D120 to D123 D124 to D127 D128 to D131 D132 to D135 D136 to D139 D140 to D143 35 4 Writes the display data "R" to DCRAM address 27H. 5 DCRAM data write (normal increment mode) 36 2 Writes the display data "I" to DCRAM address 28H. 5 DCRAM data write (normal increment mode) 37 9 4 DCRAM data write (normal increment mode) 38 8 5 DCRAM data write (normal increment mode) Writes the display data "X" to DCRAM address 29H. 39 0 2 DCRAM data write (normal increment mode) Writes the display data " " to DCRAM address 2AH. 40 0 2 DCRAM data write (normal increment mode) Writes the display data " " to DCRAM address 2BH. 41 0 A DCRAM data write (normal increment mode) 0 2 Writes the display data " " to DCRAM address 2CH. 42 0 2 Set AC and SC addresses 0 0 0 0 0 0 Sets AC to the DCRAM address 00H, SC to the horizontal dot address 0H and the vertical dot address 0H. Turns on the LCD for all digits (13 digits) in MDATA . LC75810E/T 43 1 4 Display on/off control F F F 1 44 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 45 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 46 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 47 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 48 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 49 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 50 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 51 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. Continued on next page. No.7141-49/54 Continued from preceding page. MSB No. LSB Instruction (hexadecimal) Display Shifts just the MDATA display three dots to the left. Operation D112 to D115 D116 to D119 D120 to D123 D124 to D127 D128 to D131 D132 to D135 D136 to D139 D140 to D143 52 0 Shifts just the MDATA display three dots to the left. C Display scroll 3 0 0 0 53 0 Shifts just the MDATA display three dots to the left. C Display scroll 3 0 0 0 54 0 C Display scroll 3 0 0 0 55 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 56 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 57 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 58 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 59 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. LC75810E/T 60 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 61 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 62 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 63 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 64 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 65 0 C Display scroll 3 0 0 0 Shifts just the MDATA display three dots to the left. 66 0 2 Set AC and SC addresses 0 0 0 0 0 0 Sets AC to the DCRAM address 00H, SC to the horizontal dot address 0H and the vertical dot address 0H. Shifts just the MDATA display two dots to the up. 67 0 C Display scroll 0 0 2 0 68 0 C Display scroll 0 0 2 0 Shifts just the MDATA display two dots to the up. Continued on next page. No.7141-50/54 Continued from preceding page. MSB No. LSB Instruction (hexadecimal) Display Shifts just the MDATA display two dots to the up. Operation D112 to D115 D116 to D119 D120 to D123 D124 to D127 D128 to D131 D132 to D135 D136 to D139 D140 to D143 69 0 Shifts just the MDATA display two dots to the up. C Display scroll 0 0 2 0 70 0 C Display scroll 0 0 2 0 71 8 4 Display on/off control 0 0 0 0 Sets to power saving mode, turns off the LCD for all digits. 72 1 4 Display on/off control F F F 1 Turns on the LCD for all digits (13 digits) in MDATA. 73 0 2 Set AC and SC addresses 0 0 0 0 0 0 Sets AC to the DCRAM address 00H, SC to the horizontal dot address 0H and the vertical dot address 0H. LC75810E/T No.7141-51/54 Notes 26: In sample 2 showing the correspondence between instructions and the display, a 13 digits x 1 line 6 x 7 dot matrix LCD is used, and CGRAM and ALATCH are not used. 27: The data format will have the following format if super-increment mode is used for the "DCRAM data write" instructions (numbers 3 to 41) in sample 2 showing the correspondence between instructions and the display. Note that the sample below shows 39 characters of DCRAM data being divided into 3 separate "DCRAM data write" instruction executions in the super-increment mode. No. DCRAM data write (super-increment mode) E DCRAM data write (super-increment mode) 3 DCRAM data write (super-increment mode) 4 5 0 2 D 4 1 4 4 5 2 5 9 4 8 4 4 4 0 2 4 4 2 5 9 4 6 5 5 4 9 5 F 4 0 2 C 4 3 4 7 3 5 LSB Instruction MSB D24 to D27 D28 to D31 D32 to D35 D36 to D39 D40 to D43 D44 to D47 D48 to D51 D52 to D55 D56 to D59 D60 to D63 D64 to D67 D68 to D71 D72 to D75 D76 to D79 D80 to D83 D84 to D87 D88 to D91 D92 to D95 D96 to D99 D100 to D103 D104 to D107 D108 to D111 3 to 15 3 5 1 4 3 8 3 16 to 28 0 2 C 4 4 2 5 29 to 41 4 4 F 4 5 0 2 No. LSB Instruction MSB Operation Writes the display data "S" "A" "N" "Y" "O" " " "L" "C" "7" "5" "8" "1" "0" to DCRAM addresses 00H to 0CH. Writes the display data " " "L" "C" "D" " " "D" "R" "I" "V" "E" "R" " " " " to DCRAM addresses 0DH to 19H. Writes the display data "D" "O" "T" " " "M" "A" "T" "R" "I" "X" " " " " " " to DCRAM addresses 20H to 2CH. D112 to D115 D116 to D119 D120 to D123 D124 to D127 D128 to D131 D132 to D135 D136 to D139 D140 to D143 LC75810E/T 3 to 15 0 0 2 A DCRAM data write (super-increment mode) 1 3 0 3 16 to 28 D 0 2 A DCRAM data write (super-increment mode) 0 2 0 2 29 to 41 0 2 2 A DCRAM data write (super-increment mode) 0 2 0 2 No.7141-52/54 LC75810-8725 Character Font (standard) Lower 4 bits Upper 4 bits MSB 0000 0011 0 n C c } m n _ o ^ G g . I IJ i ij E E I I O O U U A O A a _ n e A 1 2 3 4 5 6 7 8 9 : ; < = > ? O N M ] L l K [ k { J Z j z N I Y i y u u H X h x u u G W g w o o F V f v o o E U e u i i D T d t i i C S c s e e B R b r e e A Q a q a a @ P p a a | A A A E E I I O O U U a o a o _ n 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0001 0010 CG 0000 LSB RAM(1) 0001 (2) ! 0010 (3) " 0011 (4) / # 0100 (5) $ 0101 (6) % 0110 (7) & LC75810E/T 0111 (8) 1000 (9) AE ( 1001 (10) ae ) 1010 (11) OE * 1011 (12) oe + 1100 (13) , 1101 (14) - 1110 (15) . No.7141-53/54 1111 (16) / LC75810E/T Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, of otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of March, 2002. Specifications and information herein are subject to change without notice. No.7141-54/54 |
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